The Real Challenge of 200 mm SiC Isn't Wafer Size. It's Industrialization.
What CMP performance, engineering qualification and manufacturing economics reveal about silicon carbide's next production transition.
In this article
A 200 mm wafer offers approximately 1.78 times the geometric area of a 150 mm wafer. That is 77.8% more surface area. But area alone does not deliver more qualified devices at a competitive cost.
The silicon carbide industry is already beyond the question of whether 200 mm substrates can be manufactured. Suppliers are shipping material, device makers have released products, and new capacity is entering ramp-up.
The more important question is whether the manufacturing system can sustain quality, yield and productivity as volumes increase.
Bare-wafer chemical mechanical polishing (CMP) makes that challenge visible because its performance depends on incoming material, downstream requirements and conditions extending well beyond engineering trials.
1. CMP Makes the Industrialization Challenge Visible
A conventional monocrystalline SiC substrate passes through crystal growth, boule characterization, slicing, edge preparation, grinding or lapping, mechanical polishing, CMP, cleaning and inspection before epitaxy. Actual process sequences vary by manufacturer.
A polishing rate is meaningful only alongside the incoming wafer condition and outgoing specifications.
SiC is exceptionally hard and chemically resistant. CMP must remove damage left by earlier processing while delivering a surface suitable for epitaxial growth.
Material removal rate (MRR) matters, but so do scratches, roughness, total thickness variation (TTV), edge profile and repeatability. A faster process that creates rework, rejects or downstream defects may be a poor improvement.
A 2022 study by Sean Yu and colleagues at Applied Materials illustrates the engineering trade-off.
In their production-oriented research involving 150 mm 4H-SiC substrates, a single-wafer bulk-polishing condition achieved a Si-face MRR of 6.4 µm/h, with an average surface roughness (Ra) of 0.10 nm. The work also demonstrated a Si-face removal rate exceeding 8.5 µm/h under another condition.
These are published research results under specific experimental conditions, not representative figures for commercial 200 mm production.
The same study reported a 31% improvement in TTV across a 25-wafer evaluation.
The implication is important: wafer geometry, not merely polishing speed, influences the usable area and quality of the finished substrate.
2. A Larger Wafer Changes the Process Window
Moving to 200 mm requires more than transferring a 150 mm recipe and adjusting equipment settings.
At unchanged nominal contact pressure, for example, the total force associated with wafer area would increase as the wafer becomes larger. That creates reasons to recharacterize carrier support, pressure distribution, pad conditioning and edge behaviour rather than assuming direct recipe portability.
Incoming material may also vary in thickness, bow, warp or residual damage.
The larger diameter changes wafer-handling and inspection demands. Metrology may need renewed correlation and sampling to reveal radial defects across the full 200 mm surface.
A good measurement at the wafer centre cannot substitute for a reliable full-wafer distribution.
Equipment architecture introduces another engineering decision.
Revasum offers a 200 mm-capable single-wafer polishing platform with integrated cleaning and individual wafer processing. Large-format batch and double-side polishing approaches are also commercially available.
Single-wafer systems can offer greater individual process control, while batch configurations can provide parallel processing capacity.
Neither architecture can be declared universally superior without considering quality requirements, effective throughput, equipment availability, consumables and cost per accepted wafer.
A 200 mm-capable machine is not, by itself, a qualified 200 mm manufacturing process.
3. Engineering Qualification Begins Where Demonstration Ends
From an industrialization perspective, the first question I would ask is whether the manufacturing team has clearly defined what a successful outgoing wafer actually means.
Surface roughness alone is insufficient.
The qualification baseline may include defect classifications, subsurface damage, wafer geometry, contamination and downstream epitaxial requirements, supported by reliable measurement methods.
The next question concerns the process window.
Design of experiments (DOE) can reveal interactions between pressure, platen speed, slurry characteristics, pad condition and incoming material. Failure mode and effects analysis (FMEA) helps prioritize the risks associated with these interactions.
Measurement system analysis (MSA) is equally important. Without reliable measurement capability, teams may mistake inspection variation for process improvements or deterioration.
Qualification evidence must extend beyond a limited number of successful wafers.
It needs to address representative materials, multiple lots, relevant equipment variation, controlled process recipes and abnormal-condition reaction plans.
Statistical process control (SPC) helps assess stability. Process-capability claims require statistically appropriate evidence.
Productivity must also be evaluated under realistic production conditions, including cleaning, handling, maintenance and equipment interventions.
The objective is not simply to qualify a recipe. It is to qualify a controlled manufacturing process.
Public semiconductor roadmaps reinforce this distinction.
In its 2023 Bucheon expansion announcement, onsemi stated that its manufacturing line would start with 150 mm wafers and transition to 200 mm upon qualification of the new SiC process. That was the company's announced plan at the time, not confirmation that the conversion was subsequently completed.
Infineon Technologies has similarly described a phased transition toward 200 mm, with qualification playing a central role in its manufacturing roadmap.
These announcements show that qualification is not merely an administrative milestone. It determines when a technology can progress toward industrial deployment.
A successful wafer demonstrates technical possibility. Qualification establishes evidence of repeatability under defined conditions.
Sustaining that performance in daily manufacturing remains another challenge.
4. Change Management Is an Engineering Discipline
A wafer-diameter transition affects people and systems that may never interact directly with the polishing recipe.
Procurement must ensure material and consumable compatibility. Equipment engineering must control machine configurations. Maintenance must adapt preventive actions, spare parts and intervention procedures.
Quality teams need reliable inspection criteria and escalation rules. Operations must have stable work instructions, qualified personnel and clear reaction plans.
Production planning must understand actual capacity across the complete manufacturing flow, including metrology and cleaning.
Consider an illustrative scenario.
A new CMP recipe achieves its removal-rate and surface-quality targets during engineering trials. During production ramp-up, incoming-wafer variation increases, pad-conditioning frequency changes and inspection capacity struggles to keep pace.
The recipe may still perform as intended under its original trial conditions, yet accepted output deteriorates.
The challenge now extends beyond polishing chemistry. It involves suppliers, maintenance, metrology, engineering and production management.
This is why effective industrial change management requires more than communication and training.
It requires clearly assigned technical ownership, controlled equipment and recipe configurations, documented qualification evidence, coordinated supplier changes and defined production-release decisions.
The operating organization must also be able to detect abnormal conditions, react consistently and prevent recurrence.
Industrialization is not complete when engineering hands over the process. It must continue until the organization can sustain its performance.
5. The Economics Are Decided by Accepted Wafers
Material removal rate describes how quickly material is removed.
It does not tell us how many wafers a tool completes per hour, how many meet specification or what those accepted wafers cost.
Handling, cleaning, downtime, inspection, consumables, rework and yield all influence the final result.
Consider a simplified, hypothetical single-wafer example.
A stable process operates with a 15-minute effective cycle time, 80% productive utilization, $35 in variable cost per wafer and a 95% accepted-wafer yield.
Assume a fully burdened equipment and factory cost of $300 per hour.
Under these assumptions, the process delivers 3.2 processed wafers per hour, with a calculated cost of approximately $135.53 per accepted wafer.
Now reduce the cycle time to 10 minutes while maintaining the same utilization.
Equipment output increases to 4.8 processed wafers per hour.
However, if variable cost increases to $55 and accepted yield falls to 78%, the cost rises to approximately $150.64 per accepted wafer.
The cycle becomes one-third shorter, while the cost per accepted wafer increases by approximately 11%.
These values are entirely illustrative. They are not actual operating results or disclosed manufacturing costs from any SiC producer.
The example demonstrates why a process cannot be evaluated on MRR alone.
A full industrial business case should include depreciation, equipment availability, consumables, maintenance, breakage, rework, inspection, qualification costs and factory-level capacity constraints.
SEMI standards E10, E79 and E35 provide established frameworks for evaluating equipment reliability, productivity and cost of ownership.
The relevant manufacturing decision is therefore not necessarily which process removes material the fastest.
It is which qualified process delivers the required surface quality and accepted output at the most competitive total cost.
6. Industry Milestones Reveal Different Levels of Maturity
Recent semiconductor announcements illustrate how many stages separate technology development from mature manufacturing.
In September 2024, Coherent Corp. announced that shipments of its 200 mm SiC substrates and epitaxial wafers were underway.
In February 2025, Infineon Technologies announced that its first SiC products manufactured using 200 mm wafer technology would be released to customers during the first quarter.
In September 2025, Wolfspeed commercially launched its 200 mm SiC materials portfolio and offered 200 mm epitaxial wafers for customer qualification.
Each represents an important industrial milestone, but material availability, customer product release and manufacturing qualification are not equivalent achievements.
STMicroelectronics provides another useful example.
In its second-quarter 2026 financial filing, the company reported that its new 200 mm SiC manufacturing activities in Catania, Italy, had started and entered the ramp-up phase.
The filing also discussed start-up costs associated with newly integrated manufacturing activities.
That is an important distinction. Manufacturing start-up and the subsequent ramp are separate stages of industrial development.
The public filing does not establish the plant's specific CMP recipes, wafer yields or unit manufacturing costs.
The final test comes after equipment commissioning and engineering qualification, when the complete factory must sustain output under normal operating conditions.
A first wafer is a milestone. A high polishing rate is a process achievement. A successful qualification lot provides valuable technical evidence.
But industrial maturity requires stable quality, predictable output, available equipment, controlled variation and competitive manufacturing economics.
Conclusion — From Process Capability to Industrial Performance
The promise of 200 mm SiC is real. Its industrial advantage, however, will not be determined by wafer diameter alone or by the highest polishing rate demonstrated in a controlled experiment.
It will be determined by whether the complete manufacturing system can repeatedly deliver the required quality, throughput, yield and cost under actual production conditions.
This requires engineering qualification, disciplined change management, equipment and supplier readiness, and sustained operational control.
That is where process engineering becomes industrialization.
Anas BOURAS
Founder — ALFABE Design & Engineering
Engineering | Industrialization | Manufacturing Performance
References
- Yu, S., et al. (2022). Highest Quality and Repeatability for Single Wafer 150mm SiC CMP Designed for High Volume Manufacturing. Materials Science Forum, Vol. 1062, pp. 229–234. https://www.scientific.net/MSF.1062.229
- Revasum. 6EZ Silicon Carbide Polisher — Single-Wafer Processing Equipment. Manufacturer product information and technical documentation. https://www.revasum.com/
- onsemi (2023). onsemi Completes Expansion of Silicon Carbide Production Facility in Bucheon, South Korea. Official corporate announcement. https://www.onsemi.com/company/newsroom/news-and-insights/onsemi-completes-expansion-of-silicon-carbide-production-facility-in-bucheon-south-korea
- Infineon Technologies (2025). Infineon Reaches Next Milestone on 200 mm Silicon Carbide Roadmap: Product Roll-Out to Customers Starts. Official press release, February 13, 2025. https://www.infineon.com/press-release/2025/infxx202502-055
- Coherent Corp. (2024). Coherent Expands Silicon Carbide 200 mm n-Type Epitaxial Wafer Production. Official press release, September 26, 2024. https://www.coherent.com/news/press-releases/coherent-expands-silicon-carbide-epitaxial-wafer-production
- Wolfspeed (2025). Wolfspeed Announces the Commercial Launch of 200 mm Silicon Carbide Materials Portfolio. Official announcement, September 10, 2025. https://www.wolfspeed.com/company/news-events/news/wolfspeed-announces-the-commercial-launch-of-200mm-silicon-carbide-materials-portfolio-unlocking-the-industrys-ability-to-manufacture-at-scale/
- STMicroelectronics (2026). Second Quarter and Six Months Ended June 27, 2026 — Form 6-K. United States Securities and Exchange Commission, July 30, 2026. https://www.sec.gov/Archives/edgar/data/932787/000093278726000058/stm-6k_q2x2026.htm
- SEMI — E10. Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization. https://store-us.semi.org/products/e01000-semi-e10-specification-for-definition-and-measurement-of-equipment-reliability-availability-and-maintainability-ram-and-utilization
- SEMI — E79. Specification for Definition and Measurement of Equipment Productivity. https://store-us.semi.org/products/e07900-semi-e79-specification-for-definition-and-measurement-of-equipment-productivity
- SEMI — E35. Guide to Calculate Cost of Ownership (COO) Metrics for Semiconductor Manufacturing Equipment. https://store-us.semi.org/products/e03500-semi-e35-guide-to-calculate-cost-of-ownership-coo-metrics-for-semiconductor-manufacturing-equipment